Highest-throughput mixed-signal simulation with CustomSim and VCS The majority of today’s designs contain significant analog and mixed-signal content. Even SoCs that are designed for essentially digital functions still require PLLs for timing control, digitally-controlled power management circuits, and high-speed I/O devices. To complete verification of SoCs that contain a combination of RTL and synthesized logic, along with custom digital and analog circuits; Discovery AMS analog/digital co-simulation provides a direct kernel integration between Synopsys CustomSim, VCS and VCS-MX. Overview Overview Discovery AMS provides a comprehensive environment that enables verification of full-chip mixed-signal designs with built-in support for Verilog-AMS language defined by the Accellera 2.0 standard. It provides a unique combination of accuracy, performance and capacity with the flexibility of simulating design abstractions in any combination of Verilog, VHDL, SPICE, Verilog-A and Verilog-AMS.